William E. Ayer Professor of Electrical Engineering, Stanford University
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Principal investigator on the monolithic 3D chip project
A team from Stanford, Carnegie Mellon, Penn, and MIT built a true 3D chip stacking memory directly on logic at a U.S. commercial foundry. Presented at December's IEEE electron devices conference, it beats conventional flat chips by 4x in tests and could deliver 1,000x energy efficiency gains in future generations. It uses carbon nanotube transistors and resistive RAM built at low temperatures, creating vertical data highways instead of today's horizontal crawl.
Updated May 16
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